Custom IO ========= 28 IO can be customized as LVDS or CMOS level. HSEC8_ASIC_BUFFER IO is configured on MATIS board (see schematics for more details) +--------+---------------+----------------+--------------+--------------------+ | POWER | | LVDS | | LVDS Buffer | Buffer CMOS | | | | | (max9157) | | AVC4t245 | | | +--------+-------+-------+------+---------+------+-------+--------------------+ | PGOOD | DE | RE* | OE* | DIR | OE* | DIR | Comment | +--------+-------+-------+------+---------+------+-------+--------------------+ |0 |0 |1 |1 | |1 | |Tri-state | +--------+-------+-------+------+---------+------+-------+--------------------+ |1 |0 |0 |0 |0 |1 | |LVDS: ASIC to FPGA | +--------+-------+-------+------+---------+------+-------+--------------------+ |1 |1 |1 |0 |1 |1 | |LVDS: FPGA to ASIC | +--------+-------+-------+------+---------+------+-------+--------------------+ |1 |0 |1 |1 | |0 |0 |CMOS: ASIC to FPGA | +--------+-------+-------+------+---------+------+-------+--------------------+ |1 |0 |1 |1 | |0 |1 |CMOS: FPGA to ASIC | +--------+-------+-------+------+---------+------+-------+--------------------+ The buffers’ outputs is directly connected to the FPGA with CMOS 1.8 Volt. .. list-table:: :widths: 25 25 25 25 :align: center :header-rows: 1 * - Signal name - FPGA bank - FPGA pin - IO level * - FMC_ASIC_BUFFER_1 - 35 - A4 - CMOS18 * - FMC_ASIC_BUFFER_2 - 34 - T2 - CMOS18 * - FMC_ASIC_BUFFER_3 - 34 - T1 - CMOS18 * - FMC_ASIC_BUFFER_4 - 35 - N4 - CMOS18 * - FMC_ASIC_BUFFER_5 - 34 - U2 - CMOS18 * - FMC_ASIC_BUFFER_6 - 34 - U1 - CMOS18 * - FMC_ASIC_BUFFER_7 - 34 - R3 - CMOS18 * - FMC_ASIC_BUFFER_8 - R2 - U1 - CMOS18 * - FMC_ASIC_BUFFER_9 - 34 - N3 - CMOS18 * - FMC_ASIC_BUFFER_10 - 34 - N1 - CMOS18 * - FMC_ASIC_BUFFER_11 - 34 - P1 - CMOS18 * - FMC_ASIC_BUFFER_12 - 34 - J6 - CMOS18 * - FMC_ASIC_BUFFER_13 - 34 - N6 - CMOS18 * - FMC_ASIC_BUFFER_14 - 35 - N5 - CMOS18