Principle
=========

.. figure:: boards.png
    :figwidth: 70 %
    :align: center


    Boards

The test bench consists of three boards:

*  ZedBoard: Using a  Xilinx Zynq®-7000 SoC, it provides all necessary interfaces to control the others boards like ethernet connection, I2C interface, power supply
*  MATIS board:
*  ASIC board: 


.. figure:: matis.png
    :figwidth: 100 %
    :align: center


    Functional scheme

FMC connector
-------------

.. list-table:: FMC connector pins
   :widths: 25 25
   :align: center
   :header-rows: 1


   * - Pin
     - Function

   * - VCC_ASIC_LOGIC
     - Regulated voltage

   * - VCC_ANALOGIQUE_ASIC_1
     - Regulated voltage

   * - VCC_ANALOGIQUE_ASIC_1
     - Regulated voltage
    
   * - VCC_12V
     - 12 V from main power, fuse protected
   
   * - ASIC_SDA and SCL
     - IC2 link

   * - RESET_ASIC
     - Pull down by default.

   * - SC_ASIC
     - :doc:`slowMatis`

   * - LVDS_CLK_TO_ASIC
     - Clock from FPGA to ASIC

   * - TRIGGER_TO_ASIC
     - :doc:`injection`

   * - TRIGGER_FROM_ASIC
     - :doc:`triggerFPGA`

   * - HSEC8_ASIC_BUFFER
     - :doc:`customIO`
    
   * - INJ_DETECTOR
     - :doc:`injection`

   * - INJ_NS
     - :doc:`injection`

   * - ASIC_DATA
     - Data from ASIC connected to ADC

   * - DAC_ASIC
     - :doc:`refDAC`



I2C link
--------

The link is splitted in 2 channels:

* S0 : control the components of the MATIS board
* S1 : control for the ASIC board

.. figure:: i2c.png
    :figwidth: image
    :align: center


    I2C link