Principle

Boards

The test bench consists of three boards:

• ZedBoard: Using a Xilinx Zynq®-7000 SoC, it provides all necessary interfaces to control the others boards like ethernet connection, I2C interface, power supply

• MATIS board:

• ASIC board:

Functional scheme

FMC connector

FMC connector pins

Pin	Function
VCC_ASIC_LOGIC	Regulated voltage
VCC_ANALOGIQUE_ASIC_1	Regulated voltage
VCC_ANALOGIQUE_ASIC_1	Regulated voltage
VCC_12V	12 V from main power, fuse protected
ASIC_SDA and SCL	IC2 link
RESET_ASIC	Pull down by default.
SC_ASIC	Slow control
LVDS_CLK_TO_ASIC	Clock from FPGA to ASIC
TRIGGER_TO_ASIC	Injection
TRIGGER_FROM_ASIC	Trigger to FPGA
HSEC8_ASIC_BUFFER	Custom IO
INJ_DETECTOR	Injection
INJ_NS	Injection
ASIC_DATA	Data from ASIC connected to ADC
DAC_ASIC	Reference to DAC

I2C link

The link is splitted in 2 channels:

• S0 : control the components of the MATIS board

• S1 : control for the ASIC board

I2C link